1. Field of the Invention
The embodiments of the invention generally relate to semiconductor wafers and, more particularly, to semiconductor wafer structures and methods of forming the structures that balance variations in reflectance and absorption characteristics.
2. Description of the Related Art
Semiconductor wafer fabrication often involves the use of a rapid thermal anneal (RTA) process to affect the electrical properties of active devices on the wafer. More specifically, an RTA process can be used to activate dopants, diffuse dopants, anneal structures, repair damage from ion implantation processes, etc. RTAs are typically performed by powerful halogen lamp-based heating equipment, flash lamps, or lasers which direct radiation onto a wafer surface in order to change the wafer temperature. However, variations in the reflectance and absorption in different regions of a wafer, e.g., due to different materials and/or different thicknesses of materials, can result in non-uniform temperature changes across the wafer. These non-uniform temperature changes can result in temperature variations on the wafer of 10° C. or more.
Variations in reflectance and absorption characteristics can be caused by a variety of different factors including, different materials, the patterns of those materials in different regions of a wafer and the thicknesses of those materials in different regions of the wafer. For example, dielectric materials, such as silicon dioxide, in shallow trench isolation structures have different reflectance and absorption characteristics than silicon materials incorporated into devices. Dense regions of a wafer (i.e., regions of a wafer having a high number of devices) will have a higher silicon to silicon dioxide ratio than less dense regions. Different silicon to silicon dioxide ratios in different regions of the wafer will result in non-uniform temperature changes during an RTA. These non-uniform temperature changes can cause variations in dopant activation, dopant diffusion, damage repair, etc. across the wafer and can, thereby, cause variations in threshold voltages, sheet resistances, drive currents, leakage currents, etc. between devices on different regions of the wafer. Thus, non-uniform temperature changes can cause significant, location-dependent, variations in device performance.
Furthermore, as technologies continue to scale, anneal ramp times will continue to decrease (e.g., to sub-second ramps) and these faster ramp times will be accompanied by an even greater sensitivity to variations in reflectance and absorption characteristics across a wafer.